JPH0511331B2 - - Google Patents
Info
- Publication number
- JPH0511331B2 JPH0511331B2 JP61141339A JP14133986A JPH0511331B2 JP H0511331 B2 JPH0511331 B2 JP H0511331B2 JP 61141339 A JP61141339 A JP 61141339A JP 14133986 A JP14133986 A JP 14133986A JP H0511331 B2 JPH0511331 B2 JP H0511331B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- block
- data
- invalid
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61141339A JPS62298850A (ja) | 1986-06-19 | 1986-06-19 | バツフアメモリ装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61141339A JPS62298850A (ja) | 1986-06-19 | 1986-06-19 | バツフアメモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62298850A JPS62298850A (ja) | 1987-12-25 |
JPH0511331B2 true JPH0511331B2 (en]) | 1993-02-15 |
Family
ID=15289655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61141339A Granted JPS62298850A (ja) | 1986-06-19 | 1986-06-19 | バツフアメモリ装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62298850A (en]) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011022746A (ja) * | 2009-07-15 | 2011-02-03 | Renesas Electronics Corp | キャッシュメモリのデータ入れ替え方法 |
-
1986
- 1986-06-19 JP JP61141339A patent/JPS62298850A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS62298850A (ja) | 1987-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1124888A (en) | Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability | |
JPS61195441A (ja) | 自動更新する単純化キヤツシユ | |
JPH0616272B2 (ja) | メモリアクセス制御方式 | |
US6938118B1 (en) | Controlling access to a primary memory | |
JPH0511331B2 (en]) | ||
JPH044617B2 (en]) | ||
JPS6343774B2 (en]) | ||
JPS6255743A (ja) | キヤツシユメモリおよびこれを用いたキヤツシユメモリシステム | |
JPH1055308A (ja) | キャッシュメモリ | |
JPH0511333B2 (en]) | ||
JPS6141024B2 (en]) | ||
JPS5818710B2 (ja) | 記憶システム | |
JP3074897B2 (ja) | メモリ回路 | |
JP2021190002A (ja) | 情報処理装置及びプログラム | |
JPS62226348A (ja) | 主記憶装置兼主記憶制御装置 | |
JPS61211752A (ja) | ペ−ジ履歴メモリ装置 | |
JPH02226447A (ja) | コンピユータ・システムおよびその記憶装置アクセス方法 | |
JPH0752410B2 (ja) | キャッシュメモリ制御方式 | |
JPS63311548A (ja) | キャッシュメモリ制御回路 | |
JPH04199242A (ja) | キャッシュ記憶装置 | |
JPS6243737A (ja) | 割り込み制御方式 | |
JPS6093562A (ja) | 緩衝記憶制御装置 | |
JPH0431136B2 (en]) | ||
JPH0497459A (ja) | キャッシュ一致処理方式 | |
JPS63200251A (ja) | キヤツシユメモリ制御方法 |